1. Technical Field
The present invention relates in general to data processing, and in particular, to transactional processing in data processing systems.
2. Description of the Related Art
With the rise of multi-core, multi-threaded data processing systems, a key performance consideration is the coordination of the processing performed by multiple concurrent threads. In conventional systems, coordination of processing between threads is commonly achieved through the use of mutex (mutually exclusive) locks in memory. Typically, a mutex lock is associated with a portion of a shared data set, and prior to entering a code section that modifies that portion of the shared data set, a thread must acquire the associated mutex lock. After the code section is complete, the thread then releases the mutex lock, making it available for acquisition by the other concurrent threads.
Mutex locks thus synchronize access to the shared data set among multiple concurrent threads, but do so with significant overhead as each of the concurrent threads consumes cycles acquiring and releasing the mutex locks corresponding to various portions of the shared data set. It should also be noted that the use of mutex locks also leads to thread stalls, since a thread requiring a mutex lock held by another concurrent thread must suspend processing until the mutex lock is released by the other thread.
Another commonly employed alternative or additional technique for coordinating the processing of multiple threads is the execution of atomic memory access instruction pairs, such as load-and-reserve and store-conditional. To support atomic memory access, each processing element is equipped with one reservation register per-thread for holding the memory address of a reserved memory location. Upon execution of a load-and-reserve instruction in a thread, the load target address is recorded in the reservation register of that thread and is said to be “reserved” by the thread. While an address is reserved, storage modifying operations by other threads are monitored to detect any storage-modifying access to the reserved address, which would cancel the reservation. If no intervening storage-modifying operation is detected following establishment of the reservation and prior to execution by the reserving thread of a store-conditional instruction targeting the reserved address, the store-conditional instruction succeeds in updating the reserved address. If, however, a storage-modifying operation targeting the reserved address is detected between establishment of the reservation and execution of the store-conditional instruction, the reservation is canceled, and the store-conditional instruction fails. In this case, the reserving thread is typically programmed to loop back and again obtain a reservation for the same address.
As with lock-based thread synchronization, thread synchronization through the use of atomic memory access instruction pairs is also subject to high overhead costs. In particular, a separate reservation must be acquired (possibly many times) for each memory address to which access is synchronized, leading to substantial code overhead in cases in which access to numerous memory address is to be synchronized.
Because of the overhead concerns associated with conventional mutex locks and atomic memory access instruction pairs, recently developed multi-threaded data processing systems employ transactional processing in which a thread executes critical code sections atomically, only committing data results of a critical code section to the architected state if no other thread performs a conflicting data access during execution of the critical code section. Thus, in cases in which a conflicting data access is detected during transactional processing of a critical code section, the data processing system must discard any speculative data results obtained during execution of the critical code section and revert to the architected state of the thread.